Three Physical Constraints Are Converging in AI Datacenter Infrastructure

AI infrastructure is approaching several physical limits at once. In 2023, a typical accelerator rack consumed around 20 kW, while each chip dissipated roughly 350 watts. By 2024, rack power had reached 50 kW and chip power 700 watts. In 2025, racks reached 120 kW, individual processors exceeded 1,000 watts, and heat flux density reached 50 to 100 W/cm². The 2026 generation pushes racks to 240 kW, chips beyond 2,000 watts, and heat flux to 120 W/cm².

The next generation, already in validation at multiple hyperscalers, targets megawatt-class racks, chips rated above 3,000 watts, and heat flux densities exceeding 200 W/cm².

This is not a gradual progression. It is a step change that challenges three systems simultaneously: cooling, power delivery, and electrical interconnects. At the 2026 OCP Global Summit in San Jose, xFusion Director of Product Management Arthur Wang discussed the engineering issues in a keynote titled “Next-Generation Power & Cooling Solutions.” The central point was that these constraints are interdependent. Addressing two while neglecting the third can still leave infrastructure unusable.

xFusion describes this relationship as “computing-power synergy.” More precisely, it means co-optimizing the energy conversion chain from the grid to the transistor, with cooling, power delivery, and interconnect treated as coupled variables rather than separate procurement categories.

The thermal wall: materials science versus Moore’s Law

Air cooling is no longer sufficient for high-density AI racks. The more immediate question is how much capacity current liquid-cooling systems provide and whether they can accommodate the next generation of chips without major mechanical upgrades.

At heat flux levels above 200 W/cm², convective air cooling cannot remove heat quickly enough to prevent thermal throttling, regardless of plenum geometry or fan configuration. Direct liquid cooling, particularly cold-plate-based DLC, is therefore the practical path. However, cold-plate performance depends on its materials and microchannel geometry.

xFusion presented diamond-copper composite cold plates with equivalent thermal conductivity above 650 W/m·K, approximately twice that of pure copper at 385 to 400 W/m·K. Their fin geometries vary according to chip hot spots. The design supports an average heat flux of 200 W/cm² across the cold plate and more than 400 W/cm² at localized hot spots. Total cooling capacity for a single chip exceeds 4,000 watts.

A 4,000-watt capacity provides approximately 33 percent headroom above the projected 3,000-watt chip generation. In liquid cooling, that margin provides protection against the silicon roadmap advancing faster than the mechanical refresh cycle.

The material options presented by xFusion cover several cost and performance levels:

• Graphene thermal pads: 130 W/m·K, used to fill irregular gaps at thicknesses of 0.3 to 5 mm.
• High-density copper skived cold plates: 385 to 400 W/m·K, serving as a standard option for current-generation chip cooling.
• Liquid-metal thermal interface material: 30 W/m·K, with interface thermal resistance as low as 0.02 °C·cm²/W to reduce microscopic air gaps.
• Pure diamond cold plates: 800 to 2,500 W/m·K, intended for extreme heat spreading.
• Diamond-copper composites: 550 to 800 W/m·K, combining diamond’s thermal conductivity with copper’s machinability.

The company is also developing two-phase jet cooling. This method uses the latent heat of liquid-to-gas phase change instead of relying only on single-phase sensible heat. It can reduce coolant flow rates for a given thermal load. The remaining engineering challenges include large-scale sealing, pressure management, and blind-mate fluid connectors for serviceability.

For current deployments, xFusion’s FusionPod for AI V8 is a 42U modular liquid-cooled rack rated for up to 155 kW. It uses a distributed coolant distribution unit architecture that does not require secondary piping modifications. Retrofitting liquid cooling into an existing facility often requires new secondary coolant loops and associated floor work, which can take quarters rather than weeks. Removing that dependency can shorten deployment timelines from years to months.

The electrical wall: why 48V-class distribution does not scale to megawatt racks

Cooling and power delivery are closely linked. Every watt delivered to a chip eventually leaves the system as heat, and the electrical path from the utility transformer through conversion stages to the board-level voltage regulator loses energy along the way.

At the common 48V-class bus voltage, nominally 54V, current requirements become extreme as rack power increases:

• 10 kW rack: 185 amps
• 40 kW rack: 741 amps
• 120 kW rack: 2,222 amps
• 240 kW rack: 4,444 amps
• 500 kW rack: 9,259 amps
• 1 MW rack: 18,519 amps

Resistive copper losses follow the square of current. Increasing rack power 25 times, from 40 kW to 1 MW, also increases current 25 times, but increases resistive losses 625 times. At 1 MW per rack with 54V distribution, busbar copper losses alone can exceed 50 kW. The busbars may also weigh more than 200 kg per rack, creating structural and thermal challenges.

The basic solution is to increase the distribution voltage. Moving from 54V to 800V DC, an increase of approximately 14.8 times, reduces current by about 15 times and I²R losses by approximately 220 times. The number of power-conversion stages can also fall from four in legacy AC/54V architectures to three. This raises end-to-end efficiency from roughly 88 percent to above 90 percent and reduces line losses from 5 to 8 percent to below 1 percent.

xFusion is developing an 800V HVDC Sidecar prototype for rack configurations ranging from 300 kW to 1.2 MW. Its roadmap also includes a direct 800V HVDC architecture that removes additional conversion stages and supports integration with green power sources.

The voltage transition depends partly on advances in power semiconductors. xFusion is applying wide-bandgap devices across the conversion stack:

• SiC MOSFETs for AC-to-HVDC rectification, using PFC and LLC topologies at 100 to 300 kHz.
• GaN HEMTs for HVDC-to-DC conversion, using LLC resonance at 800 kHz to 1 MHz.
• GaN-based multiphase voltage regulators for the final 54V-to-12V/6V stage at 500 kHz to 1 MHz.

Higher switching frequencies allow smaller magnetic components and greater power density, both important as rack space becomes increasingly constrained.

The company is also developing vertical power delivery, which places conversion modules directly behind the chip package instead of routing current laterally across the motherboard. This can shorten the power path by approximately 90 percent, reducing resistive losses and transient-response problems when a processor changes its current draw by hundreds of amps within microseconds.

The interconnect wall: copper at 224G and beyond

The third constraint is electrical signaling. Copper traces operating at 224 Gbps per lane are already close to their signal-integrity limits. Channel loss, insertion loss, and crosstalk at these frequencies require extensive equalization and error correction. At higher speeds, copper becomes increasingly difficult to use.

Optical interconnects are beginning to address this limitation. Co-packaged optics, which place photonic engines directly on or beside switch silicon, reduce the distance penalty associated with electrical signaling and provide greater bandwidth density than copper backplanes. In AI training clusters with thousands of accelerators operating in tightly coupled scale-up domains, interconnect bandwidth affects both the size of distributed jobs and the efficiency of inference distribution.

xFusion has commercially deployed 224G high-density orthogonal backplanes and is conducting pre-research on 448G. Its Super Node architecture is an open-architecture, liquid-cooled system that delivers up to 240 kW per rack, supports 128 XPU per cabinet and 256 XPU across dual cabinets, and is designed for compatibility with multiple processor vendors.

This approach addresses the fragmentation of the accelerator market. A proprietary interconnect fabric can create a dependency on a single vendor, while a multi-vendor design provides a different path for managing processor and supply-chain changes.

The compound problem

Cooling, power, and interconnect constraints are arriving in the same product generations. They also influence one another, making partial solutions risky.

A high-performance liquid-cooling system paired with legacy 54V power delivery may be limited by electrical losses before the coolant reaches its thermal capacity. An 800V DC system connected to an insufficient optical fabric may leave accelerators waiting for data. A high-bandwidth network behind a thermally throttled compute tier cannot use its full capacity.

This is the basis for treating cooling, power, and interconnect as a single optimization problem extending from the grid to the chip. xFusion’s work spans thermal-interface materials and cold plates, board- and rack-level power conversion, cabinet-scale liquid cooling, and backplane interconnects.

The company participates in more than 60 industry organizations, contributes to more than 60 open standards, and has an ecosystem of more than 30,000 partners worldwide. These activities reflect the need for coordination across multiple suppliers and standards as AI infrastructure converges.

At OCP, Wang summarized the issue as follows: “In the Agentic era, competitiveness is not about how many chips you have. It is about how much real business value you can extract from every watt and every joule of heat.”

The value chain presented by xFusion was WATT → FLOPS → TOKEN → AGENT → VALUE. Each stage introduces conversion losses, so facility performance cannot be measured only by power consumption. It must also be evaluated by the useful outcomes produced from that energy.

Under this model, an AI datacenter is an energy-conversion system as much as it is a building for computers. Cooling, power delivery, and interconnects will jointly determine how efficiently future systems convert electricity into computing and business results.