A Decade In, zeroRISC Sees a Bright Future for Open Silicon

At the Hot Chips conference in 2018, Google hardware engineers described the recently introduced Titan chip, which was designed to establish a silicon root of trust (RoT) in servers. RoT was part of a broader effort by processor designers to strengthen security following the Spectre and Meltdown vulnerabilities. Google engineers also discussed plans to make the technology available as an open-source offering, adding momentum to the emerging open-silicon movement.

Dominic Rizzo led Google’s OpenTitan effort and served as its technical lead manager for five years.

“The way I sold OpenTitan inside Google was they were buying a lot of heterogeneous hardware for the cloud and it made their security posture a little lumpy,” Rizzo says. “OpenTitan was really the first truly credible, well-resourced, do-it-right-from-scratch open-source silicon project.”

For Rizzo, OpenTitan became the starting point for a decade-long effort to advance open silicon. He left Google in 2023 but continues to serve as project director for OpenTitan at lowRISC, the project’s official maintainer and host. That same year, Rizzo co-founded zeroRISC, where he is now CEO. The startup focuses on encouraging broad commercial adoption of open-silicon roots of trust.

Building an open silicon ecosystem

In May, zeroRISC and other industry participants, including Qualcomm, Analog Devices, and Meta, as well as the Max Planck Institute for Security and Privacy, launched Pavona under the auspices of GlobalPlatform, a nonprofit standards consortium. Rizzo chairs Pavona, which is intended to provide a neutral ecosystem for designing open and secure hardware.

Pavona is structured in a way that is comparable to how the open-source Yocto Project and Zephyr Project support software development. It includes a production-stage post-quantum cryptography (PQC) stack supporting algorithms such as ML-KEM, ML-DSA, and SLH-DSA. It also provides a composable platform that organizations can use to build hardware roots of trust and chip subsystems.

Rizzo says the arguments for open silicon largely parallel those for open-source software. Potential benefits include reducing costs by avoiding licensing fees and royalties associated with commercial chips from companies such as Intel, AMD, and Nvidia, reusing infrastructure, and improving collaboration. Open development can also support faster innovation, greater transparency and trust across the supply chain, and broader participation in design. More people reviewing designs can provide additional opportunities to identify and correct vulnerabilities and defects.

The concept of open-source silicon emerged around the same time as open-source software and Linux, Rizzo says, but it did not initially gain comparable momentum.

“It has a lot to do with inconsistent interfaces, inconsistent standards, the fact that roles for engineers in the silicon industry are very specific,” he says. “There's a backend production person, there's a layout person, there's an analog person, there's a digital designer, there is a DV person. It's not like software. There is not really that kind of movement within those roles. They get very, very specialized, so this notion of ‘there's this open project that does all these things, leverage it how you will,’ that never really took off. There's also a lot fewer people who do it than do software.”

According to lowRISC, changes in the semiconductor industry have helped support the recent expansion of open silicon. One factor has been the adoption of the intellectual property business model.

“All chip designs today are modular, and the vast majority adopt third-party IP from IP vendors like Arm and Synopsys, and foundries like TSMC,” lowRISC wrote earlier this year. “This IP reuse has brought to the industry a major reduction in development cost and time and increase in quality, which are benefits typically associated with open source. ... It is only a small step for silicon vendors to start using open-source IP instead of that from commercial vendors.”

The open RISC-V architecture has also matured since its introduction in 2010. It is widely used in embedded systems, while efforts continue to bring it into the datacenter.

“RISC-V almost gave permission because RISC-V is an open-source instruction set architecture,” Rizzo says. “Even before, when those things were all super proprietary, Arm famously made quite a bit of money off proprietary ISAs, but what that did is ask the natural question: If you've got an open-source ISA, why not open-source implementation? That's a natural next step. That granting of permission helped a lot as well.”

lowRISC’s Ibex CPU was released in 2019 and is now used in various system-on-chip designs.

Nuvoton brought a discrete RoT security chip based on OpenTitan to market in 2024 and announced Google’s plans to use it in Chromebooks running ChromeOS.

In 2025, the first release of Caliptra arrived. The RoT architecture includes OpenTitan elements and was developed through the CHIPS Alliance and Open Compute Project by companies including Microsoft, Google, AMD, and Nvidia. It is designed for datacenter-level SoCs.

Expanding participation and security work

More companies and industry groups have entered the open-silicon field in recent years. lowRISC was launched in 2014, while SiFive, which provides custom silicon solutions based on RISC-V, emerged from stealth two years later.

The Capability Hardware Enhanced RISC Instructions Alliance, or CHERI, was founded in 2024. Its members include Arm, Google, the UK National Cyber Security Centre (NCSC), and lowRISC. CHERI aims to protect data stored in hardware memory by incorporating security mechanisms into hardware.

zeroRISC also focuses on security through what it calls a “silicon trust stack.” Its offerings include a Pavona repository and collaboration layer for chip design teams, with version control, review workflows, and build artifacts. The platform also includes continuous integration with verification workloads for physical hardware and post-quantum-ready silicon IP.

A provisioning service includes a line-side server for datacenters backed by a hardware security module (HSM). A management service provides OEM debugging and over-the-air updates.

In May, zeroRISC unveiled the open-source release of its cryptographic hardware and software stack for classical and post-quantum environments. The stack includes a configurable Cryptolib embedded library in its silicon platform, a programmable asymmetric cryptography coprocessor (ACC) for post-quantum and classical asymmetric algorithms, and dedicated hardware accelerators for symmetric operations such as AES and SHA2/3.

The post-quantum transition

PQC is a central challenge for the industry and organizations such as Pavona, according to Rizzo. Governments in the United States, Europe, and elsewhere are establishing aggressive deadlines for organizations to adopt technologies intended to address the emergence of quantum computing.

Quantum systems are expected to be capable of rapidly decrypting data protected by AES-256 and similar encryption methods. Organizations with access to such systems could potentially decrypt data they previously stole but could not access at the time, a threat known as “harvest now, decrypt later.”

Google has placed that timeframe as early as 2029, while other organizations are considering 2030 or later. Rizzo describes the transition to PQC as a major change that may occur only once in a generation. Adoption is beginning with algorithms including ML-DSA, ML-KEM, and SPHINCS+, with additional algorithms expected to follow.

“PQ cryptography, it's a bit more of a pain to implement than the classical cryptography because in classical cryptographic, you have one hard problem that tends to be at the root of all of these cryptographic operations and primitives, especially for asymmetric” cryptography, he says. “Post-quantum cryptography does not work the same way and the trade-offs are a lot more varied and the underlying hard problems are different, and then the implementations for the different operations are themselves also different.”

Long-term governance and responsibility

Several issues still need to be addressed. Pavona’s work includes IP, block design, and development, but substantial effort is also focused on infrastructure, configurability, and flexibility so organizations can more easily use open-silicon technologies. Governance is another important concern.

“That’s one of the more interesting aspects of this whole thing because we can build the technology in the open,” Rizzo says. “We understand how to do that. It's more like, how do you sustain it for the long term? How do you build the real ecosystem around it? How do you make it so that everyone benefits to some degree, not just a single supporter?”

New regulations, including the European Union’s Cyber Resilience Act, are also shifting liability for cyber incidents toward device makers. This is prompting manufacturers to examine what they implement and what they are responsible for, while looking more deeply into their supply chains to gain greater control over the products they build.

“You need to have a hardware root of trust below the software that you can reset back to a known good state or all hope is lost,” Rizzo says. “That’s dawning on people. You need to actually have control over the chips. The software attack surface has always been large, but now the attack capability has grown to match that large surface. The way you address that is you have a silicon root of trust.”