Addressing Agentic AI Fleet Challenges with the NVIDIA Vera CPU

AI factories are interconnected systems whose fleet economics depend on how efficiently the full stack converts power and capital into completed agent tasks. GPUs execute models, while CPUs manage orchestration, tool execution, and sandboxed computation.

Agentic workloads differ from conventional computing because their runtime profiles are unpredictable and highly variable. Telemetry from 163,594 agentic sessions showed that more than 97% had unique trajectory profiles (Figure 1). This variation makes it impractical to size a fleet around several specialized CPU designs.

Production telemetry also shows a common execution pattern: a long sequential reasoning chain interrupted by occasional bursts of parallel work. The sequential path is latency-bound and controls overall session completion time. Short fan-out phases, meanwhile, require both available thread concurrency and low latency for each thread.

Rather than designing separate fleet segments for isolated tool-calling scenarios, AI factories require a balanced CPU design point. The NVIDIA Vera CPU is designed to provide strong per-core performance for typical agentic workloads while also handling intermittent parallel bursts. The following sections examine agent trajectories and the role of this balance in fleet efficiency.

Optimizing the Critical Path of Agentic Trajectories

An agentic trajectory can be described by its length and width (Figure 2):

• Length: The number of reasoning steps, tool calls, retries, and subtasks required to resolve a turn.
• Width: The amount of work that fans out at each stage, including concurrent tool calls, retrieval operations, sandboxes, and sub-agents.

A session can have substantial width while still spending most of its wall-clock time waiting on the sequential chain. Parallel bursts are temporary, but the dependency chain continues throughout the run. Per-thread latency remains important even during fan-out because the main agent often waits for parallel tasks to finish before proceeding.

A CPU fleet must therefore support both dimensions of the workload. It needs enough concurrency to absorb parallel bursts and strong per-thread performance to accelerate the sequential path that determines end-to-end completion time.

For this reason, the relevant optimization target for an agentic CPU fleet is the number of completed user sessions, not simply the number of cores. Systems with high core counts may appear efficient, but achieving core-density targets can require sacrificing the single-thread performance needed to reduce critical-path latency.

Agentic workflows are affected when sequential, latency-sensitive tasks run on lower-performance cores or when synchronization overhead increases across large, heterogeneous clusters. A balanced agent-focused CPU combines sufficient cores for concurrent tool execution and sub-agent fan-out with strong single-thread performance for the sequential steps that dominate total latency.

What Real Agent Sessions Look Like

Real agent telemetry illustrates this pattern. In the Claude Code session shown in Figure 3, the main agent followed a long sequential trajectory during most of the 33-minute run.

The data shows both major characteristics of agentic workloads: significant fan-out and a long dependency chain. Sub-agent activity produces bursts of parallel work that must be handled quickly, while the overall user turn proceeds through an ordered main trajectory in which each step enables the next. The CPU fleet therefore needs sufficient concurrency for fan-out and strong per-thread performance on the latency-sensitive path.

A CPU can temporarily reduce the number of active cores to increase single-thread performance. However, this can leave 8 GB of memory per core unused and create a substantial memory total cost of ownership penalty. Figure 4 illustrates a 256-core CPU with 64 active cores and 192 inactive cores, leaving up to 1.5 TB of attached memory stranded.

A balanced CPU design optimizes the entire trajectory rather than one phase in isolation. Strong per-thread responsiveness, meaningful concurrency, adequate memory bandwidth, and efficient power use help maximize completed user turns while making effective use of CPU cores, DRAM, GPU HBM, and the broader memory hierarchy.

How Vera CPUs Provide This Balance

The NVIDIA Vera CPU uses NVIDIA Olympus cores designed to maintain strong per-thread performance while the complete CPU is active. Its wide front end, advanced branch prediction, deep out-of-order execution, and high-bandwidth memory subsystem help cores maintain progress across large code bases, branch-heavy control flow, dynamic runtimes, and dependency-heavy execution.

The Claude Code telemetry demonstrates why agentic workloads require this combination: concurrency is needed for fan-out, while per-thread speed keeps the dominant sequential path moving.

Estimated SPEC CPU® 2026 results in Figure 5 evaluate this design point across workloads relevant to agentic computing, including compiler, static-analysis, and Python benchmarks. The results show loaded per-core performance and indicate that the NVIDIA Vera CPU delivers up to 1.5x the agentic performance of the latest competition.

A Single CPU Design Point for Agentic Fleets

The NVIDIA Vera CPU is intended to provide a common CPU foundation for the varied trajectories found in agentic AI fleets. Strong single-thread performance at full-socket load supports the latency-sensitive sequential path, while high concurrency and memory bandwidth handle intermittent tool-call and sub-agent fan-out. Its low-latency monolithic architecture is designed to reduce topology-related stalls and variability across these phases.

This balance can help limit stranded resources. Cores remain useful during sequential work and parallel bursts, while memory attached to those cores is less likely to remain tied to underused compute. It also reduces the need to divide a fleet among multiple specialized CPU designs for unpredictable tool-calling patterns.

The resulting platform is designed to convert compute capacity, memory bandwidth, and power into more completed agent turns across large AI factory deployments.

Performance and Measurement Notes

NVIDIA Vera SPEC CPU® 2026 results were measured internally in July 2026. The results and configurations are described in the NVIDIA Vera CPU Whitepaper. AMD Venice results are based on a published result. Individual Venice workload performance was estimated from a SPECrate®2026_int_base score of 2070, with components normalized using internal Turin measurements. Results may vary.

SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation.