Qualcomm Validates HBC Stacked Memory Ahead of 2027 Dragonfly AI250 Sampling

Qualcomm has completed the initial validation of its High Bandwidth Compute (HBC) memory architecture, a technology planned for the company’s Dragonfly data center AI accelerators. HBC stacks multiple DRAM layers above a small compute die, bringing memory closer to the hardware that accesses it. Qualcomm expects this arrangement to improve energy efficiency and reduce some production costs.

The validation moves HBC closer to commercial deployment. Products using the technology are scheduled to begin sampling in 2027. Qualcomm says its testing confirmed that HBC works and delivers energy efficiency and memory bandwidth near its targets. The results support the company’s plans to move toward mass production while continuing development of the Dragonfly AI250 accelerator and later products.

HBC Uses Near-Memory Compute to Reduce Data Movement

Qualcomm first announced HBC during its 2026 Investor Day. The architecture is designed to balance memory capacity, performance, and manufacturing cost by using near-memory compute.

HBC is related to high-bandwidth memory (HBM) and other stacked-memory technologies, but its structure differs. HBM stacks multiple DRAM dies above a base die, which connects to the host processor through an ultra-wide memory bus. HBC instead places a small compute die beneath the memory stack.

This arrangement can reduce energy use because moving data consumes energy, and longer data transfers generally consume more. Placing memory directly above a compute die shortens the connection compared with HBM and external memory such as LPDDR5X. The resulting energy savings could be used to improve chip performance or enable more chips to operate within the same power budget.

The HBC compute die is not a complete processor. It is intended to handle memory-bandwidth-intensive operations and send the resulting data to a larger compute die at the center of the processor. This brings selected memory and compute functions closer together.

Qualcomm is also targeting lower packaging costs. HBM’s wide memory bus requires advanced packaging technologies such as CoWoS or EMIB to connect memory stacks, compute dies, and memory controllers. By moving much of the relevant computation to the die beneath the memory, HBC needs less bandwidth between that die and the larger processor die elsewhere in the package. Qualcomm says this connection could therefore use less expensive technologies, including traditional 2D organic substrates.

HBC does not remove all manufacturing challenges. Like HBM, it requires multiple DRAM dies, or wafers in Qualcomm’s implementation, to be bonded above another die using through-silicon vias (TSVs). The complexity is reduced, however, because the demanding die-to-die connectivity is minimized, leaving memory stacking as the primary advanced packaging requirement.

The architecture also aims to balance bandwidth and capacity. Qualcomm’s design uses LPDDR5X DRAM dies rather than the thinner, high-performance dies used by HBM. The company has not disclosed final performance figures, but it projects that an HBC stack will offer more capacity than current HBM4 implementations.

Qualcomm’s stated objective is to provide a broader balance than HBM, on-die SRAM, or off-package LPDDR. HBC is intended to offer substantially more bandwidth than external LPDDR5X and approach HBM performance, while avoiding the capacity limitations of on-die SRAM and some of the cost associated with HBM-based designs.

The overall goal is to build AI inference accelerators that meet the technology’s requirements for both memory bandwidth and capacity, with fewer trade-offs than existing memory architectures.

Validation Results: Two-Layer Stack Delivers Five Times the Bandwidth per Watt of HBM4

For the initial validation, Qualcomm connected an early HBC sample stack to a test system at its San Diego laboratories.

The tested component used two DRAM layers. Commercial products are expected to use four layers, so the validation did not yet cover the full-sized stack planned for shipping products.

Qualcomm used an automated tester to measure the sample as both an LPDDR5X device and an HBC device. The company reported three main findings:

1. The HBC architecture operated successfully, demonstrating that the design can be implemented.
2. On a bandwidth-per-watt basis, the HBC solution delivered more than five times the energy efficiency of HBM4 according to HBM4’s published specifications.
3. Although Qualcomm did not disclose absolute bandwidth figures, it classified the measured bandwidth as 18 times higher than external LPDDR5X.

The result was below Qualcomm’s initial projection of a sixfold advantage over HBM4. Even so, the reported figure would represent a substantial efficiency improvement if it carries over to a complete product.

Qualcomm said its validation also covered thermal behavior, but it has not released additional details. Thermal management remains an important technical issue because the more active compute die at the base of a stacked-memory structure is expected to generate more heat.

Dragonfly AI250 Sampling Planned for 2027

With the initial HBC validation complete, Qualcomm is moving toward commercialization through the Dragonfly AI250 accelerator. The AI250 follows the Dragonfly AI200 accelerator, which is due this year, and is expected to be the first product to integrate HBC. The technology is also planned for future Qualcomm AI accelerators.

AI250 does not yet have a launch date. Qualcomm says sampling will begin in the first half of 2027, potentially earlier than the company’s initial schedule, which placed sampling later in the year.

HBC is not expected to remain limited to Dragonfly products. Qualcomm has previously said that it plans to bring the technology to consumer-focused Snapdragon products, although it has not identified specific products or timing.

The architecture is intended to improve energy efficiency and reduce total cost of ownership for Qualcomm’s AI inference products. If the technology performs as projected, Qualcomm expects it to support accelerators that are less expensive to build and operate than contemporary designs. The next major test will come as Dragonfly AI250 moves toward sampling in the first half of 2027.