IBM, AMD, and Oak Ridge Introduce a Quantum Error-Correction Platform

Quantum computing researchers have made progress on the central challenge of correcting errors in quantum systems. Solving that challenge is necessary before practical, commercial fault-tolerant quantum computing can become viable.

Researchers are pursuing several approaches, including error-correction codes running on quantum processing units (QPUs) with different grid designs, decoders operating on a single CPU, and AI reinforcement learning. These efforts share two goals: reducing the number of errors and lowering the technical overhead required to support larger, more affordable systems.

Logical qubits, which combine multiple physical qubits, are an important part of error reduction, but additional advances are needed. Current quantum systems typically experience one gate error for every 100 to 1,000 operations. Fault-tolerant systems require a significant improvement in that rate. Qubits are extremely fragile and can decohere, losing their quantum properties because of noise from sources including light, sound, and the activity of other qubits.

A co-designed quantum and classical platform

IBM, AMD, and the Quantum Science Center at Oak Ridge National Laboratory have introduced a co-design platform for quantum error correction. The platform combines quantum computing with classical high-performance computing systems located at the same facility.

According to IBM, this arrangement is uncommon. Quantum and classical systems are often connected through cloud services and APIs, which can add complexity and latency. Close physical integration is intended to let the systems work together more directly.

“In order to experiment with these techniques and build algorithms, quantum and classical processors need to be able to work closely together,” said Seetharami Seelam, Distinguished Engineer and chief architect of classical system co-design for quantum-centric supercomputing.

Quantum systems are expected to operate alongside traditional supercomputers in hybrid environments, with QPUs serving as another type of accelerator alongside GPUs, TPUs, and other processors. AI is expected to help connect the systems, while researchers investigate how generative and agentic AI can be used in quantum-classical environments.

“The collaboration will also focus on exploring how AI can develop more effective algorithms and workflows, as well as advancing error correction through both new methods and improvements to existing approaches,” Seelam said. “The GPUs that are part of the co-design platform will play a key role in running the AI models or algorithms that scientists plan to develop and improve upon.”

The platform will be housed at IBM’s facility in Poughkeepsie, New York. It will include IBM quantum computers, particularly the 120-bit Nighthawk r2 quantum chip, and Oak Ridge’s Umbra HPC system. Umbra is powered by AMD’s fifth-generation Epyc “Turin” Epyc 9005 data center CPUs and “Antares” Instinct MI355X GPUs.

The AMD processors and accelerators will support research into quantum error correction, decoding optimization, and software orchestration.

Researchers will be able to use the integrated system to develop and test quantum-classical workflows, evaluate quantum algorithms, and study the infrastructure requirements of error-corrected quantum systems. The platform is intended to provide a foundation for developing quantum systems and software.

Nighthawk connectivity and pulse control

IBM highlighted Nighthawk’s square-lattice connectivity, which differs from the company’s earlier “heavy-hex” chip architecture. The square lattice uses a two-dimensional grid in which most qubits connect directly to four nearest neighbors, providing about a 60 percent increase in connectivity compared with heavy-hex.

The design also enables shorter execution times and compatibility with the standard surface code used for error correction. Combined with high maximum circuit speed and real-time pulse control, the system will let researchers evaluate error-correction techniques according to their qubit requirements, execution time, and classical computing needs. This could help clarify how GPUs can support quantum computing workloads.

Through IBM’s quantum API, researchers can access deep-pulse capabilities that allow qubits to be measured during a calculation and the results to be processed in real time. The API also allows precise control over the timing of signals intended to protect qubits from noise.

Exploring hierarchical error correction

One example IBM identified for further research is hierarchical error correction. This approach layers two codes: an inner code protects qubits within a module, while an outer code provides a second layer of protection.

The method can reduce hardware and connectivity requirements. IBM research indicates that it could support one trillion logical operations at a physical-qubit error rate of one error in 1,000. Because the approach depends on classical computing, the new platform will allow researchers to test it with GPUs in a low-latency environment.

The work also aligns with the US Department of Energy’s Quantum Genesis Mission, which aims to develop fault-tolerant quantum systems. In July, IBM and the University of Chicago conducted experiments involving up to 70 logical qubits and 438 hard operations, according to Seelam.

“The Quantum Genesis Mission’s Q Competition targets 100 logical qubits running 100,000 such operations by late 2028,” Seelam said. “To reach this goal, the broader quantum community needs to achieve a 238-fold increase in hard operation count, and we need to do it fast. We believe this goal is feasible, but achieving it will require progress across several areas and close collaboration among industry, national laboratories and government researchers.”

Seelam said the integrated platform will provide resources for testing systems against the Quantum Genesis Mission’s objectives. IBM also plans to apply work from the platform to the development of its Quantum Starling system, which the company expects to deliver as a fault-tolerant computer by 2029.